1. Field of the Invention
The present invention relates, in general, to an output driver controller, and more particularly to a controller for controlling the data output driver of a synchronous semiconductor memory device.
2. Description of the Related Art
Generally, in a synchronous semiconductor memory device (hereinafter, simply referred to as a “memory device”), data input and output timing is controlled using an internal clock which is synchronized to an external clock. As is well known in the art, a DLL circuit is a circuit that is most widely used to generate an internal clock synchronized to an external clock.
It is normal that a memory device having a DLL circuit uses an internal clock outputted from the DLL circuit to control data input and output timing.
FIG. 1 is a block diagram for explaining data output operations of a conventional memory device having a DLL circuit.
A DLL circuit 100 is a circuit which outputs an internal clock for controlling the internal operation of a memory device using an external clock.
An output driver 110 is a circuit which outputs to the outside the data read from the inside of the memory device.
An output driver controller 120 is a circuit which controls the operation of the output driver 110. The output driver 110 is enabled while the output signal from the output driver controller 120 maintains an enable state, and is disabled while the output signal from the output driver controller 120 maintains a disable state (or a reset state).
However, in the conventional art, a disable signal (that is, a reset signal) is outputted from the output driver controller 120 while the output driver controller 120 is not operated, and if a read command is applied for data reading, in response to the read command, the output driver controller 120 escapes from the disable state and outputs an enable signal.
Therefore, in the conventional art, a problem is caused in that the operational state of the output driver 110 is determined by the output driver controller 120 irrespective of the state of the output signal from the DLL circuit 100, whereby data output timing can be made unclear.